1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a double pixel gate in panel (DGIP) type LCD device and a method of driving the DGIP type LCD device.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are widely used as monitors for laptop computers and desktop computers because of their high resolution, high contrast ratio, color rendering capability and superiority in displaying moving images. An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image. An LCD device includes a liquid crystal display (LCD) panel having two substrates and a liquid crystal layer interposed therebetween and a backlight assembly supplying light to the LCD panel. The liquid crystal molecules are aligned along the direction of an electric field generated between electrodes formed on the two respective substrates of the LCD panel. By refracting and transmitting incident light from a backlight assembly below an LCD panel and controlling the electric field applied to a group of liquid crystal molecules within particular pixel regions, a desired image can be obtained.
Of the different types of known liquid crystal display (LCD) devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subjects of significant research and development because of their high resolution and superior ability in displaying moving images.
FIG. 1 is a schematic block diagram showing a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display (LCD) device includes an LCD panel 10 and a driving circuit unit 20. The LCD panel 10 displays images and the driving circuit unit 20 supplies several electric signals for displaying images to the LCD panel 10.
The LCD panel 10 includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates. Gate lines 12 and data lines 14 are formed on the first substrate, which is referred to as an array substrate. The gate line 12 crosses the data line 14 to define a pixel region “P.” A thin film transistor (TFT) “T” is connected to the gate line 12 and the data line 14, and a pixel region connected to the TFT “T” is formed in the pixel region “P.” A color filter layer including red, green and blue color filters is formed on the second substrate, which is referred as to a color filter substrate. A common electrode is formed on the color filter layer. The liquid crystal layer constitutes a liquid crystal capacitor “Clc” with the pixel electrode and the common electrode.
The driving circuit unit 20 includes an interface 22, a timing controller 24, a gate driver 26, a data driver 28, a reference voltage generator 30 and a source voltage generator 32. The interface 22 transmits signals from an external driving system such as a computer to the timing controller 24. The timing controller 24 treats the signals to supply a data signal, a data control signal and a gate control signal to the gate and data drivers 26 and 28. The gate and data drivers 26 and 28 are connected to the gate and data lines 12 and 14, respectively. The gate driver 26 generates a gate signal for turning on/off the TFT “T” of the LCD panel 10 using the gate control signal from the timing controller 24, and the gate lines 12 are sequentially enabled by the gate signals in each frame. The data driver 28 generates gamma voltages using the data signal and the data control signal from the timing controller 24, and the gamma voltages are supplied to the data lines 14. As a result, when the TFT “T” is turned on by the gate signal, the gamma voltage corresponding to the data signal is supplied to the corresponding pixel electrode through the TFT “T,” and an electric field generated between the pixel electrode and common electrode drives the liquid crystal layer.
The reference voltage generator 30 generates a gamma reference voltage for a digital to analog converter (DAC) of the data driver 28. In addition, the source voltage generator 32 generates a source voltage for elements of the driving unit 20 and a common voltage for the LCD panel 10.
In an LCD device, when a direct current (DC) voltage is applied to the liquid crystal layer for a long time section, polar impurities in the liquid crystal layer are fixed to interfaces between the liquid crystal layer and one of the first and second substrates due to the electric field. Accordingly, a pretilt angle of the liquid crystal molecules is changed and the liquid crystal layer is not controlled as required, which deteriorate the display quality. To prevent the above deterioration, the LCD device is driven by an inversion method where the polarity of the data signal is inverted in each frame.
FIG. 2 is a timing chart showing signals supplied to a liquid crystal display device according to the related art. In FIG. 2, a common voltage “Vcom” is applied to a common electrode and a gate signal “Vgate” is applied to the gate lines. In addition, a data signal “Vdata” is applied to the data lines and is transmitted to pixel electrodes so that the pixel electrode has a pixel voltage. In the gate signal “Vgate” having a rectangular wave shape, a gate-high voltage “Vgh” and a gate-low voltage “Vgl” are alternately repeated. The gate-high voltage “Vgh” and the gate-low voltage “Vgl” correspond to a turn-on time section and a turn-off time section, respectively. The data signal “Vdata” has opposite polarities in two sequential frames. Accordingly, the data signal “Vdata” has a positive polarity (+) during the tth frame, while the data signal “Vdata” has a negative polarity (−) during the (t+1)th frame.
In addition, when the gate signal “Vgate” is changed from the gate-high voltage “Vgh” to the gate-low voltage “Vgl” at a border between the turn-on time section and the turn-off time section, the capacitance of the liquid crystal capacitor “Clc” and the pixel voltage are changed due to the charge re-distribution among the TFT “T,” the liquid crystal capacitor “Clc” and a storage capacitor (not shown). A difference in the pixel voltage may be expressed as the following equation.ΔVp=[Cgd/(Clc+Cst+Cgd)](Vgh−Vgl),where ΔVp is a pixel voltage difference, Clc is a capacitance of the liquid crystal capacitor, Cst is a capacitance of the storage capacitor, Cgd is a capacitance of the parasitic capacitor of the TFT, and Vgh and Vgl are the gate-high voltage and the gate-low voltage, respectively.
The pixel voltage difference “ΔVp” has a deviation according to the position of the pixel electrode in the LCD panel. Accordingly, the pixel voltage is asymmetrically distorted due to the non-uniform pixel voltage difference “ΔVp,” which causes the deviation in brightness. As a result, a display quality is degraded due to deterioration such as a flicker. To prevent the deterioration such as a flicker, a driving method where the gate signal “Vgate” is modulated according to a flicker signal having a rectangular wave shape has been suggested. In the driving method using a flicker signal, a rear portion of the gate signal “Vgate” in the turn-on time section has a voltage value lower than the gate-high voltage “Vgh” so that the pixel voltage difference “ΔVp” can be reduced.
An LCD device having a relatively low cost has been the subject of recent research and development. For the purpose of reducing the production cost, an LCD device having a reduced number of driving integrated circuits (ICs) has been suggested. For example, the reduction in the number of driving ICs may be obtained by reducing the number of data lines. Accordingly, a double pixel gate in panel (DGIP) type LCD device, where two adjacent pixel electrodes are connected to a single data line, has been suggested.
FIG. 3 is a schematic view showing a DGIP type LCD device according to the related art. In FIG. 3, a sub pixel region “Psub” and a pixel region “P” are defined in an LCD panel. Red, green and blue colors are displayed in three adjacent sub pixel regions “Psub,” respectively, and the three adjacent sub pixel regions “Psub” constitute a single pixel region “P.” The sub pixel regions “Psub” are arranged in a stripe shape where the subs pixel regions “Psub” displaying red “R,” green “G” and blue “B” colors are sequentially repeated along a pixel row and the sub pixel regions displaying the same color are arranged along a pixel column in the LCD panel.
In addition, two adjacent sub pixel regions “Psub” along the pixel row have a single data line in common, and two gate lines are disposed between two adjacent sub pixel regions “Psub” along the pixel column. For example, the pixel row is disposed between the mth and (m+1)th gate lines “Gm” and “Gm+1” and between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” while the (m+1)th and (m+2)th gate lines “Gm+1” and “Gm+2” are adjacent to each other without the pixel row.
In the LCD panel, a gate signal is sequentially supplied to the gate lines “G1, . . . , Gm, Gm+1, Gm+2, . . . ” and a TFT connected to the selected gate line is turned on. Accordingly, a data signal is supplied to the data lines “D1, D2, D3 . . . ” and the sub pixel regions “Psub” are driven by the data signal to display a corresponding color.
FIG. 4 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to the related art. As shown in FIGS. 3 and 4, the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are supplied to the mth, (m+1)th, (m+2)th and (m+3)th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively. The pixel regions “P” in the pixel row may be classified into odd pixel regions “Po” and even pixel regions “Pe” with the left outermost pixel column as a reference. Accordingly, in the pixel row between the mth and (m+1)th gate lines “Gm” and “Gm+1,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are driven by the mth gate signal “Vgm” of the mth gate line “Gm.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are driven by the (m+1)th gate signal “Vgm+1” of the (m+1)th gate line “Gm+1.” Similarly, in the pixel row between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are driven by the (m+2)th gate signal “Vgm+2” of the (m+2)th gate line “Gm+2.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are driven by the (m+3)th gate signal “Vgm+3” of the (m+3)th gate line “Gm+3.”
The mth and (m+2)th gate signals “Vgm” and “Vgm+2” have a time difference of one period “T,” and the (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” have a time difference of one period “T.” In addition, the mth and (m+1)th gate signals “Vgm” and “Vgm+1” have a time difference of a half period “T/2.” As a result, the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1, “Vgm+2” and “Vgm+3” are sequentially delayed by the half period “T/2.”
The mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are modulated according to a flicker signal “FLK” to prevent deterioration such as a flicker. Since the flicker signal “FLK” is synchronized with the mth gate signal “Vgm,” the mth and (m+2)th gate signals “Vgm” and “Vgm+2” having the one period “T” are modulated such that rear portions “a” of the mth and (m+2)th gate signals “Vgm” and “Vgm+2” in the turn-on time section have a voltage value lower than the gate-high voltage “Vgh.” As a result, the deterioration such as a flicker is prevented in the sub pixel regions “Psub” connected to the mth and (m+2)th gate lines “Gm” and “Gm+2.” However, the (m+1)th and the (m+3)th gate signals “Vgm+1” and “Vgm+3,” which have a time difference of the half period “T/2” with respect to the mth and (m+2)th gate signals “Vgm” and “Vgm+2,” respectively, are modulated according to the flicker signal “FLK” such that front potions of the (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” in the turn-on time section have a voltage value lower than the gate-high voltage “Vgh.” The deterioration such as a flicker is not prevented by the gate signal modulation in the front portion of the turn-on time section. Instead, the gate signal modulation in the front portion of the turn-on time section causes brightness reduction in the sub pixel regions “Psub” connected to the (m+1)th and (m+3)th gate lines “Gm+1” and “Gm+3,” thereby degrading the display quality.